In NAND flash memories, bit errors occur due to read-disturb, program-disturb, or data retention, etc. Compared to the error bits occurred in the NAND flash memories, NOR flash memories may have less error bits. To correct the bit errors, error correction codes (ECC) are used.
Miniaturization of non-volatile semiconductor memory devices or adoption of multi-level storage technology therein may cause bit errors. Thus the number of error correction bits for ECC may increase. An increase in the number of error correction bits may cause an expansion of an ECC circuit and an increase in time for coding and decoding of ECC.
Related art is disclosed in Japanese Laid-open Patent Publication No. 2008-123330, Japanese Laid-open Patent Publication No. 2000-298992, etc.